We provide web interface access to our generator for customized DFT hardware. A simple web form allows the user to specify parameters that control tradeoffs between area and speed. From the parameters, the Verilog code is generated and can be downloaded and used under the included license. Go to the DFT website.
We have developed algorithms and tools that generated multiplier blocks that multiply by one or several constants "multiplierless," that is, using only additions, subtractions, and shifts. Go to the multiplierless website.
We provide web interface access to our generator for customized DCT hardware. A simple web form allows the user to specify parameters that control tradeoffs between area and speed. From the parameters, the Verilog code is generated and can be downloaded and used under the included license. Go to the DCT website.
We provide a web interface to our generator for multiplierless finite impulse response (FIR) and infinite impulse response (IIR) filters.
We develop FPGA implementation of a class of structured LDPC codes and analyze these codes. Go to the LDPC site.