DFT IP Generator

Explanation

The SPIRAL DFT IP Generator is a fast generator for customized Discrete Fourier Transform (DFT) soft IP cores. The user has control over a variety of parameters that control the functionality of the generated core as well as parameters that control resource tradeoffs such as area and throughput. Below the input form, the resource usage is dynamically estimated and displayed. For more information, please see the references below.

Note: The below web-based generator is a prototype. We have developed a considerably improved generator (see the benchmark and first reference below) that produces better IP cores.

Generator

Input: parameters controlling DFT size, data width, twiddle width, data ordering, scaling mode, parallelism p, twiddle storage method, FIFO threshold

Output: synthesizable Verilog for an n-point DFT with parallelism p

Benchmarks

Here are a few example benchmark of the latest iteration of our generator (an improvement and considerable extension of the one above).

DFT 1024, fixed point, throughput and latency:

DFT 256, floating point, throughput:

2-D DFT 256 x 256, fixed point, throughput:

FPGA accelerated software on the FPGA's embedded PowerPC processor. Both software and hardware are generated (see [2]):

References

Peter A. Milder, Franz Franchetti, James C. Hoe and Markus Püschel
Formal Datapath Representation and Manipulation for Implementing DSP Transforms
to appear in Proc. Design Automation Conference (DAC), 2008
Markus Püschel, Peter A. Milder, and James C. Hoe
Permuting Streaming Data Using RAMs
submitted for patent application
Paolo D'Alberto, Franz Franchetti, Peter A. Milder, Aliaksei Sandryhaila, James C. Hoe, Jeremy Johnson, José M. F. Moura, Markus Püschel
Generating FPGA-Accelerated DFT Libraries
Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) 2007
Peter A. Milder, Franz Franchetti, James C. Hoe and Markus Püschel
Discrete Fourier Transform Compiler: From Mathematical Representation to Efficient Hardware
CSSI Technical Report #CSSI-07-01, Carnegie Mellon University, 2007
Peter A. Milder, Mohammad Ahmad, James C. Hoe and Markus Püschel
Fast and Accurate Resource Estimation of Automatically Generated Custom DFT IP Cores
Proc. FPGA, pp. 211-220, 2006
Grace Nordin, Peter A. Milder, James C. Hoe and Markus Püschel
Automatic Generation of Customized Discrete Fourier Transform IPs
Proc. Design Automation Conference (DAC), pp. 471-474, 2005

More publications on IP cores for FPGAs/ASICs

More publications on the discrete/fast Fourier transform

Online software generator for the discrete/fast Fourier transform

More information

Contact: Peter Milder: pam [AT-SIGN] ece [DOT] cmu [DOT] edu