Benchmarks: SPIRAL Generated Programs

On this website we collect a few benchmarks including relevant papers. See also our collection of code and our online generator.

Note that in all benchmarks shown, Spiral code was generated ("push-button"), i.e., written by a computer. Learn about the current Spiral system.

On the left side we consider the discrete Fourier transform only but different parallel platform paradigms:

SMP (Multicore)/Vector code (code using SIMD short vector instructions and multiple threads for recent chip multiporcessors)
Code for GPUs (Graphical Processing Units)
Cell processor code
Distributed memory parallel code (code for clusters)
Verilog for FPGAs
FPGA accelerated software

On the right side we consider different numerical kernels

Walsh-Hadamard transform
FIR filters
Viterbi decoding
Other functionality

SMP (Multicore)/Vector Code

Our generated multi-threaded code uses a fast barrier.

4-way vectorized, up to 4 threads:

2-way vectorized, up to 4 threads:

4-way vectorized:

4-way vectorized (all small sizes):

4-way vectorized (split-complex format):

References

Franz Franchetti and Markus Püschel
SIMD Vectorization of Non-Two-Power Sized FFTs
Proc. International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2007
Franz Franchetti, Yevgen Voronenko, and Markus Püschel
FFT Program Generation for Shared Memory: SMP and Multicore
Proc. Supercomputing (SC) 2006
Franz Franchetti, Yevgen Voronenko, and Markus Püschel
A Rewriting System for the Vectorization of Signal Transforms
Proc. High Performance Computing for Computational Science (VecPar) 2006
Franz Franchetti and Markus Püschel
Short Vector Code Generation for the Discrete Fourier Transform
Proc. International Parallel and Distributed Processing Symposium (IPDPS) 2003
Franz Franchetti and Markus Püschel
A SIMD Vectorizing Compiler for Digital Signal Processing Algorithms
Proc. International Parallel and Distributed Processing Symposium (IPDPS) 2002

IPP is Intels' vendor library. FFTW is available online.

Graphics Processing Unit (GPU)

this is work in progress ...

Cell Processor

this is work in progress ...

The code was generated on a cell simulator and run on a real cell chip at Mercury by Robert Cooper.

Distributed Memory Parallel (Cluster)

References

(Best paper award) Andreas Bonelli, Franz Franchetti, Juergen Lorenz, Markus Püschel, Christoph W. Ueberhuber
Automatic Performance Optimization of the Discrete Fourier Transform on Distributed Memory Computers
to appear in Proc. International Symposium on Parellel and Distributed Processing and Applications (ISPA) 2006

FFTW is available online.

Verilog for FPGAs

Online generator and references

FPGA Accelerated Software

Paolo D'Alberto, Franz Franchetti, Peter A. Milder, Aliaksei Sandryhaila, James C. Hoe, Jeremy Johnson, José M. F. Moura, Markus Püschel
Generating FPGA-Accelerated DFT Libraries
Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) 2007

Walsh-Hadamard Transform

FIR Filters

IPP is Intel's vendor library.

Viterbi Decoding

This is work in progress: our code does not yet include the traceback.

Karn's Viterbi implementation is available at http://www.ka9q.net/code/fec/

Other Kernels

Our work on other functionality is not yet included in the Spiral program generation framework. Please visit our software site or our hardware site or check representative publications or jump directly to one of the following: